Talk:Zilog Z8000

"Normal" memory address range?

So, the Z8001 has 7-bit segment registers that extend RAM out to 8MB (64KB per segment x 128 segments...).

And Pole Position uses Z8002s with a "smaller" memory range (how small?).

But... what does the Z8000 itself manage? As it's 16 bit, did the original authour thus imply 64KB? (Not really very much for a 16-bit class CPU) ... Or does it inherently have SOME ability to use multiple segments... just not 128 of them? 193.63.174.211 (talk) 16:42, 20 May 2014 (UTC)

How's this processor architecture? There's no info on register structure, instruction structure, anything...

Example code

It would be nice to add an example subroutine, such as the strtolower() example used for some of the other microprocessors (e.g., 6502, 80386, 68000, etc.). — Loadmaster (talk) 17:35, 22 May 2018 (UTC)

"24-bit external address bus to allow it to access up to 8 megabytes of memory"

24 bit allows access to 16 mega-words of address space, so at least 16 MiB. Why does the text only say 8MB? 91.89.172.255 (talk) 15:39, 4 January 2021 (UTC)

IBM PC reasons

I don't quite get what is the connection between this text from article "But the Z8000's launch date placed it between the 16-bit Intel 8086 (April 1978), and the Motorola 68000 (September 1979), the latter of which had a 32-bit instruction set architecture and was roughly twice as fast" and the quote from Federico Faggin.
So what if it was launched between i8086 and MC68000?
IBM PC was launched in 1981 with a very short design cycle - so all processors were available for IBM, irrespective of their release date.89.136.36.50 (talk) 19:46, 21 December 2021 (UTC) Apass

"...it required two chips to do what the 8086 did with one."

"The 8010 was eventually released almost a year later, and even then it required two chips to do what the 8086 did with one." This can't be right: the 8086 multiplexes the part of the address pins with the data pins as well, and also requires an additional chip to demultiplex them. See: Intel 8086#Buses and operation. Irdc-nl (talk) 09:48, 18 November 2025 (UTC)

Just like the 8086, the Z8001 multiplexes 16 of its address and data pins. So just like the 8086, it would require a couple of 74LS373 chips to demultiplex.

The 8086 inherently can allocate up to 64K blocks on 16 byte boundaries. Smaller blocks likewise can be allocated on 16 byte boundaries. The maximum waste is 15 bytes.

The Z8001 without its Z8010 MMU is super clunky in the way it allocates its memory. Every 64K block has to start on a 64K boundary, though there are 127 64K blocks available. Smaller blocks have to be combined and shoehorned into 64K blocks potentially wasting a kilobytes of memory. Once the Z8010 is added, the Z8001 can allocate up to 64K blocks on 256 byte boundaries, wasting no more than 255 bytes. So the Z8001 requires another big 48-pin chip to efficiently allocate memory. RastaKins (talk) 14:29, 18 November 2025 (UTC)