Talk:National Semiconductor SC/MP

xgistor.ath.cx & Sipke de Wal

Did anyone make a copy of Sipke de Wal's website before his (and its) demise?

Did anyone download his SC/MP emulator?

If anyone can help I would like to reconstruct his website as it was referenced by a lot of web-pages including this one.

From archive.org: http://web.archive.org/web/20050203210606/http://xgistor.ath.cx/scmp.htm has the text, but not the images. Google cache similarly has the text but no images. I did a quick images.google.com search for "scmpscrn", but no luck. --Mike Van Emmerik 22:07, 30 August 2006 (UTC)

Thanks, I've in fact already reconstructed that webpage (there's only one image that I'm not sure about). It was real1y the other pages and his directories of downloadable files (like his SC/MP emulator) that I can't find. The web.archive has files using the name of the zip files etc, but upon downloading them you find you've just got a file containing a message saying this file hasn't been archived ! :-( --AGoon 10:47, 1 September 2006 (UTC)

Have reconstructed his page including Elector SC/MP project simulator and NIBL simulators. --AGoon 02:34, 4 October 2006 (UTC)

External links modified (February 2018)

Hello fellow Wikipedians,

I have just modified one external link on National Semiconductor SC/MP. Please take a moment to review my edit. If you have any questions, or need the bot to ignore the links, or the page altogether, please visit this simple FaQ for additional information. I made the following changes:

• Added archive https://web.archive.org/web/20070927224715/http://www.bitsavers.org/pdf/national/_dataSheets/SCMP_dataSheet.pdf to http://www.bitsavers.org/pdf/national/_dataSheets/SCMP_dataSheet.pdf

When you have finished reviewing my changes, you may follow the instructions on the template below to fix any issues with the URLs.

This message was posted before February 2018. After February 2018, "External links modified" talk page sections are no longer generated or monitored by InternetArchiveBot. No special action is required regarding these talk page notices, other than regular verification using the archive tool instructions below. Editors have permission to delete these "External links modified" talk page sections if they want to de-clutter talk pages, but see the RfC before doing mass systematic removals. This message is updated dynamically through the template {{source check}} (last update: 5 June 2024).

• If you have discovered URLs which were erroneously considered dead by the bot, you can report them with this tool.
• If you found an error with any archives or the URLs themselves, you can fix them with this tool.

Cheers.—InternetArchiveBot (Report bug) 07:53, 14 February 2018 (UTC)

One more SC/MP SBC computer

If I'm not mistaken, Elektor (a magazine dealing with electronics, still alive) proposed a DYI (soldering required) and mail order single board comp. Here it is : https://www.elektormagazine.fr/magazine/elektor-264/60879 77.136.66.154 (talk) 20:39, 28 December 2024 (UTC)

The INS807x SC/MP-III is quite a bit different from the earlier INS8050/8060

... and this article makes no mention of that. The 8070 has a "flat" 16 bit address space (none of the 4 bit page/12 bit address stuff). It also has a proper stack with PUSH, POP instructions, a stack based subroutine call instruction, and uses the stack to push the current PC for interrupts. It also has 16 bit double precision arithmetic instructions and (gasp!) real hardware multiply and divide instructions. It clearly has some similarities to its ancestors, but the INS807x is a fairly nice chip to program. ~2025-31276-02 (talk) 18:15, 4 November 2025 (UTC)

It's worth noting hat the INS8050/8060 NIBL BASIC takes 4K of ROM, but the INS8073 BASIC only needs 2.5K for pretty much exactly the same functions. Clearly the 8070 instruction set got a lot better.

And a side note - I don't think the INS8074/5 with the 4K internal ROM ever existed outside of a databook. Has anybody actually seen one of these parts? And I'd love to know if the 4K 8075 N^2 NIBL BASIC was ever actually released. SpareTimeGizmos (talk) 18:20, 4 November 2025 (UTC)

Transistor count

I'd like to add the SC/MP to the Transistor count article. How many transistors does it have?

Ideally we would cite that number to the manufacturer -- but did Nat Semi publish the transistor count or gate count? Even if not, are the die photos in the manuals or the die photo already in this article (by @User talk:Birdman86 -- thank you!) clear enough for someone to get a reasonable estimate of the transistor count? --DavidCary (talk) 23:08, 10 December 2025 (UTC)

Bit-serial ALU claim

The main page states that the SC/MP used a bit-serial ALU for cost reasons. This appears to be unsourced. National Semiconductor datasheets and the SC/MP Technical Description do not describe the ALU this way, and published die shots have also been argued to suggest otherwise.

Should this claim be removed unless a reliable source can be provided, or supported with a citation? OldCPUs (talk) 23:14, 7 April 2026 (UTC)

It's not something National is going to brag about but the datasheet tells tales. The SC/MP takes 19 "microcycles" to do an 8-bit ADC with each microcycle being two clocks. So 38 clocks to do an 8-bit add. The 8080's slowest 8-bit ADD takes seven clocks. A 6502 immediate ADD takes two clocks. With the SC/MP's horrid efficiency, tell me how it could not be bit-serial? RastaKins (talk) 00:29, 8 April 2026 (UTC)

@RastaKins Thanks for taking the time to reply ... it's great to see detailed discussion of the SC/MP.

I agree that the SC/MP is significantly slower than contemporaries such as the 8080 and 6502, and that this performance difference is worth documenting in the article.

Other documented design choices, such as its simple control logic and built-in multi-processor bus arbitration, might also account for the higher microcycle counts.

However, concluding from instruction timing that the ALU must be bit-serial appears to be original research (see WP:OR and WP:SYNTH). Without a reliable source explicitly stating this, we shouldn't present it as fact. Such reasoning belongs on the talk page rather than being stated as fact in the article.

National Semiconductor's official documentation (SC/MP Technical Description and datasheets) consistently describes arithmetic and logic operations as standard 8-bit operations, with carry generated from the MSB and flags based on the full 8-bit result. These primary sources do not describe a bit-serial ALU.

It's also worth noting that, based on currently available sources, we cannot definitively determine whether the ALU was internally bit-serial or not. The absence of such a description does not prove the implementation either way. However, this uncertainty reinforces that we should not state the bit-serial claim as fact without a reliable source (per WP:V and WP:NOR).

Additionally, a comp.arch post (13 October 1997, “SC/MP (1977 microprocessor) architecture”) reports that a National Semiconductor designer attributed the relatively low performance to the “conditionally executed” microcode approach, rather than a bit-serial ALU. While this is not a high-quality secondary source, it does suggest an alternative explanation.

Given that the bit-serial claim currently lacks a reliable supporting source and instead relies on inference from timing, I think it should be removed in line with Wikipedia's verifiability and no-original-research policies (and left here instead).

Additional note for future readers of this thread (not part of the reply above):

• very simple control logic that uses a “conditionally executed” microcode approach (with very few branches), as described by a National Semiconductor designer who worked on the chip;
• built-in daisy-chain bus arbitration via the ENIN/ENOUT signals, which adds extra internal states to nearly every memory access so multiple processors can share the same bus with almost no external hardware;
• published die shots (the low-resolution one included in the SC/MP Technical Description manual and later higher-resolution examples made available in the community) have been argued to show an ALU section that occupies significant die area, which is inconsistent with the extremely compact layout expected of a minimal bit-serial ALU.

OldCPUs (talk) 08:39, 11 April 2026 (UTC)

@OldCPUs, your post made me try to shoot down your claim but I an edging over to your side. The best source of SC/MP info is SCMP Technical Description, Jan76. The block diagram on Page 1-0 is somewhat misleading but there's a much better block diagram on 1-12. It hints that there is a parallel ALU. But there's more evidence.

Check out the bus utilization chart on page A-2. It really shows some stunning inefficiency: 6 machine cycles or 12 clocks just to fetch an immediate instruction on something like an ANI. It then takes another 8 clocks to complete, barely enough time to do it serially. (The 8080 executes its ANI in 2 machines cycles, 7 clocks.) Look at ILD and DLD. These are the the only read-modify-write instructions. With just four clocks between the read and the write, there would not be enough time for a serial ALU to get a result.

On page 1-5 there is a photo of the chip. There is what looks like a telltale triangular carry-lookahead (CLA) array. CLAs are only needed for parallel ALUs. A look at Page 1-0 seems to indicate that this is not a CLA as the ALU is shown not adjacent to the CLA. But then again as slow as the SC/MP is, the designers probably decided to forego the CLA and just wait around for the carry to be propagated. One hint that this may be exactly the way it is implemented is ADI takes a two clocks longer than any other immediate ALU logic operation. Likewise, ADE also takes two clocks more than ANE.

My vote is to remove the claim that the SC/MP ALU is bit-serial. RastaKins (talk) 18:52, 13 April 2026 (UTC)

I have removed the unsourced bit-serial ALU claim from the lead and Bus control section, following the April 2026 discussion. The performance note is retained but now attributed only to the documented simple control logic and multi-processor features. OldCPUs (talk) OldCPUs (talk) 22:00, 22 April 2026 (UTC)

Proposed removal of Intel 8088 segmentation comparison

I plan to remove the comparison between the SC/MP address-page behaviour and Intel 8088 segmentation.

The current reference text says: "This segmented memory approach was more famous in the Intel 8088."

I do not think this comparison is helpful. The 8088 segmented model works in a different way: a logical address consists of a segment base plus an offset, from which a physical address is generated.

There is a superficial resemblance, because both systems can involve wraparound within a bounded address region, but the mechanisms are different:

• SC/MP: a 16-bit address is treated as a 4-bit page field plus a 12-bit displacement, and displacement arithmetic does not carry into the page field.
• 8088: segment:offset address translation is used to form a physical address.

For that reason, I plan to remove the 8088 comparison and describe the SC/MP behaviour directly. That keeps the useful technical point without relying on a cross-architecture analogy that may mislead readers.

OldCPUs (talk) 20:48, 30 April 2026 (UTC)

Big thumbs up from me. There was no good reason to have a 4K pages. Just a lazy program counter. RastaKins (talk) 02:31, 1 May 2026 (UTC)

Thanks @RastaKins for the removal.

Register E

You might have noticed I also kept a modified Z80 comparison: 'This use as a temporary store is loosely comparable to the alternate register set of processors such as the Zilog Z80.' I'm in two minds about whether it's actually useful... I did downgrade it from 'similar to the mirror registers' and restructured it so it's no longer tightly woven into the explanation. I wanted to check how recently it had been added before removing it, just in case it was recent. Does anyone have a view? OldCPUs (talk) 06:57, 31 May 2026 (UTC)

It would be better to lose this comparison completely. The SC/MP E register is so valuable for coding that it makes no sense not to use it so that interrupt latency can be insignificantly reduced. Heck, even my simple example code can't run in ROM without E. Moreover, E is the only register that fully supports ALU operations. It is far more comparable to the Z80 E register than A'. Z80's E can be the source for all ALU operations just like SC/MP's E. RastaKins (talk) 13:25, 31 May 2026 (UTC)

@RastaKins - Z80 comparison removed and other sections updated. OldCPUs (talk) 20:00, 1 June 2026 (UTC)

Thanks... I've enhanced the E reg description a little @RastaKins ... any suggestions of areas to focus on within E register or more generally ? OldCPUs (talk) 17:16, 2 June 2026 (UTC)

I am quite happy with the coverage of E and its many uses: stash for AC, a parameter for ALU operations, an offset for addressing, and its value as a serial register. It's a busy register! I also appreciate the comprehensive improvements you have made to the article. RastaKins (talk) 22:57, 2 June 2026 (UTC)

DMA more commonly and design intent claims

I think the current wording in the Bus control section needs to be tightened for verifiability. Two statements in particular seem to go further than the references support:

• "or more commonly a single SC/MP and related direct memory access (DMA) controllers"
• "The original idea was to ease the creation of microcontroller-like applications containing an SC/MP, one or more direct memory access (DMA) controllers, and a single shared memory."

The National Semiconductor SC/MP Technical Description clearly supports the basic technical point: the SC/MP had bus-arbitration signals that could be used for both DMA and multiprocessor operation. It lists control signals for DMA implementation and control signals for multiprocessor system implementation. It also describes bus access through an external DMA controller, and then a cascaded multiprocessor arrangement.

But, I do not see any sources supporting the comparative claim that the DMA-controller arrangement was "more common" than multiple-SC/MP operation. The National source says DMA is "frequently used" in larger systems with high-speed peripherals, but that is not the same as saying it was more common than SC/MP multiprocessor use.

The "original idea" wording also seems problematic. It attributes design intent, and frames the device as being intended for "microcontroller-like applications" built around a single SC/MP, DMA controllers and shared memory. I have not found that specific design-intent claim in the National Semiconductor material or anywhere else. The sources seem to support a neutral description of what the bus-arbitration feature allowed, rather than a historical claim about the original design motivation.

I plan to replace this with neutral wording that keeps the important technical point, while avoiding unsupported comparative and design-intent claims. If reliable sources can be found which explicitly say that DMA-controller use was more common, or that this was the original design intent, those claims should be restored with direct citations.

OldCPUs (talk) 08:03, 2 May 2026 (UTC)

Now done:

Updated the article to replace the wording discussed above. The revised Bus control section now describes the feature more neutrally as bus-access logic using bus-request, enable-input and enable-output signals, with the PMOS SC/MP names BREQ, ENIN and ENOUT and the SC/MP II / INS8060 active-low names NBREQ, NENIN and NENOUT.

The edit also removes the unsupported comparative claim that DMA-controller use was "more common", and removes the unsupported "original idea" design-intent wording. Instead, it cites National Semiconductor documentation for the PMOS SC/MP bus-access examples and the INS8060 datasheet for the corresponding SC/MP II signals. I also added Williamson and Dale for an SC/MP II / MK14-era explanation of the same DMA and multiprocessor bus-access feature.

While making the change, I corrected the earlier wording about ENOUT/ENIN. The revised text now describes bus access in terms of the processor requesting the shared bus on its bus-request line and being granted access through its enable-input line, with the active-high PMOS and active-low INS8060 signal names both noted.

This keeps the supported technical point — that the SC/MP bus-access feature could be used for DMA and daisy-chained multiprocessor arrangements — while avoiding claims about relative frequency of use or original design motivation unless better sources are found. OldCPUs (talk) 13:11, 5 May 2026 (UTC)

Updated naming for the 70-Series (INS807x family)

I have made an edit to how we refer to the later family of chips (INS8070 INS8073 etc).

Summary of the edit

- Changed the lead and the Implementations section so that **70-Series** is now the primary name (matching National Semiconductor’s own documentation).

- Kept “INS807x Series” as the alternative name in parentheses.

- Added a short, sourced note that some later sources (particularly in retrocomputing) refer to this family as “SC/MP III” or “SC/MP-3”, while clearly stating that this terminology was **not used** in contemporary National Semiconductor documentation.

Rationale

National Semiconductor’s own datasheets and user manual from the period consistently call this family the “70-Series” (or “INS8070-Series”). I felt it was more accurate to lead with the name the manufacturer actually used, rather than giving equal prominence to a later community name.

The “SC/MP III / SC/MP-3” name does appear in hobbyist, collector, and retrocomputing sources (as early as 2001), so I added a brief, attributed mention of it. However, I was careful to keep it secondary and to explicitly note that it was not used by National Semiconductor at the time.

Possible concerns I considered

My goal was to help readers understand both the manufacturer’s official name and how the chip is sometimes referred to today. I therefore kept the “SC/MP III” reference short and secondary, while leading with the official “70-Series” name in the lead and infobox.

The 2001 Japanese collector site is a personal page rather than a manufacturer source. I only used it to support the narrow point that the name has been used by some collectors since at least 2001.

One might wonder why mention the name at all if it was never official. I included it because the term has become fairly common in retrocomputing communities, and I believe documenting real-world usage (with proper attribution) is helpful for readers.

Request for feedback

Does anyone have concerns with this? I’m happy to tweak the wording, move the note to a different section, or shorten it further if that would be preferred.

OldCPUs (talk) 17:21, 4 May 2026 (UTC)

Instruction timing footnote: “22 clocks total” should be qualified or replaced

The current explanatory footnote says:

The SC/MP takes 11 "microcycles" to do an 8-bit add immediate (ADI) with each microcycle requiring two clocks, 22 clocks total. Contemporaneous CPUs are faster: The 8080's add immediate (ADI) takes seven clocks. A 6502 add immediate (ADC) takes two clocks.

I think this needs tightening. The problem is not the 11 microcycles figure, which is well supported. The problem is the conversion from microcycles to “clocks”, and especially the phrase “22 clocks total”, which is ambiguous and appears not to be the unit used in the National instruction timing tables.

The National Semiconductor SC/MP Programming and Assembler Manual gives ADI as 11 total microcycles in Appendix E.

However, the wording “each microcycle requiring two clocks” is not safe as a general SC/MP-family statement.

The original SC/MP (i.e. not SC/MP II) applications documentation defines delay timing as:

$1\ {\text{microcycle}}=2T_{X}$, where $T_{X}=1/F_{\mathrm {OSC} }$

which supports 22 oscillator cycles for an 11-microcycle instruction in that original PMOS SC/MP timing convention.

But the later INS8060 / SC/MP II data sheet defines the timing relationship differently. It states that the time interval of a microcycle is four times the period of the oscillator; that is:

period of one microcycle = $2T_{C}$

$T_{C}=2\left({\frac {1}{f_{\mathrm {OSC} }}}\right)=2\left({\frac {1}{f_{\mathrm {res} }}}\right)=2\left({\frac {1}{f_{\mathrm {XIN} }}}\right)$

where:

• $T_{C}$= time period for two cycles of on-chip or external oscillator
• $f_{\mathrm {OSC} }$ = frequency of on-chip oscillator
• $f_{\mathrm {res} }$ = resonant frequency of crystal connected between XIN and XOUT pins
• $f_{\mathrm {XIN} }$ = frequency of external clock applied to XIN pin

Therefore, for the INS8060 / SC/MP II:

ADI $=11$ microcycles $=22T_{C}=44$ oscillator cycles

At a 4 MHz oscillator, this is $44\times 0.25\,\mu {\text{s}}=11\,\mu {\text{s}}$.

This distinction matters because $T_{C}$ is not simply another name for a processor clock cycle. In the INS8060 data sheet, $T_{C}$ is introduced in the hardware timing-control discussion, after the oscillator options are described. It is an intermediate hardware timing unit derived from the oscillator, used to express microcycle and bus/input-output timing relationships. That is useful because hardware events need finer notation than the programmer-facing “microcycle”.

The comparison with the 8080 and 6502 is also slightly uneven as currently worded. Those are instruction timings stated directly in clock cycles or clock states, whereas the SC/MP sources primarily give instruction execution times in microcycles.

Interestingly, this explains why the INS8060 / SC/MP-II using a 4 MHz oscillator, compared with 1 MHz for the original PMOS SC/MP, did not make instruction execution four times faster but instead around twice as fast.

Here is a suggested replacement for the entire block mentioned in the opening of this talk topic. This keeps the sourced 11 microcycles figure, but avoids presenting 22 clocks total as though it applied unambiguously across the SC/MP family. It also avoids treating National's $T_{C}$ timing unit as equivalent to the “clock cycle” terminology used for the 8080 and 6502.

National Semiconductor's SC/MP instruction tables give ADI an execution time of 11 microcycles. In the original PMOS SC/MP timing convention, the SC/MP Microprocessor Applications Handbook defines $1$ microcycle as $2T_{X}$, where $T_{X}=1/F_{\mathrm {OSC} }$, so an 11-microcycle instruction corresponds to 22 oscillator cycles in that convention. The later INS8060 / SC/MP II data sheet uses a different timing notation: one microcycle is $2T_{C}$, and $T_{C}$ is the time period for two oscillator cycles; therefore ADI is $22T_{C}$, or 44 oscillator cycles, on the INS8060.

Does this seem a reasonable replacement? If the 8080/6502 comparison is retained, I think it should be separately cited and worded so that SC/MP microcycles, INS8060 $T_{C}$ intervals, 8080 states, and 6502 cycles are not treated as identical units.

OldCPUs (talk) 21:02, 5 May 2026 (UTC)

It is interesting that the PMOS oscillator is 1 MHz and the NMOS oscillator is 4MHz and that the NMOS has another divide stage that makes its speed only 2x instead of 4x. My comments were intended to be a bit more focused. Rather than commenting on the entire line, I was comparing only the 1976 SC/MP to its existing contemporaneous competitors which came out in 1974 and 1975. To simplify things, I compared input clocks of each to execute one specific instruction that all three support. I probably should have included the elapsed times in the note. RastaKins (talk) 14:50, 6 May 2026 (UTC)

@RastaKins Thanks for your additions of the timings... I found the references to the 6502 and 8080 but didn’t have the confidence to add the timings for those systems (the 6502 had the clock divided down internally to phi0 and phi1 .. I guess that gives it an equivenent external clock twice as fast if it wasn't internally divided... and I know zero about the 8080).

I'll update later with citations and more explanation. Thanks again!

PS I'm hoping we get the "This article is rated Start-class" to the next level! OldCPUs (talk) 19:23, 6 May 2026 (UTC)

How inefficient was the SC/MP? Very. The 4-bit COP400 from 1977 can do an 8-bit immediate add to memory faster than the SC/MP. The COP400 takes 44µS, 11 instructions, 11 bytes. (It must put the result in memory as it only has a 4-bit accumulator.) The SC/MP takes 104µS to do the same with four instructions, seven bytes. The 8080 beats both with 10.5µS, three instructions, four bytes. RastaKins (talk) 14:53, 10 May 2026 (UTC)

Montgomery Elevator / MIPROM wording

I have updated the Montgomery Elevator wording in the Uses section to keep the part that is supported by the sources, while flagging or qualifying claims that I could not verify from the cited material.

The previous wording said that Montgomery Elevator used the SC/MP as the basis for its "first micro processor based elevator controller released in 1975" and that "many" of these units were still running in buildings across the United States. I have not found a source in the current citation set that directly supports the "first" claim, the 1975 release date, or the claim that many units remain in service. I have therefore either removed those statements or marked the remaining date/priority claims with .

The replacement wording is narrower. It states that Montgomery Elevator of Moline, Illinois, later acquired by KONE in 1994, used the SC/MP in its MIPROM Hydro elevator-controller system. The KONE history page supports the 1994 acquisition by KONE. The Montgomery MIPROM brochure supports the general description of MIPROM as a "microprocessor elevator logic control" system. The later Otis PC Board Catalog gives the more specific processor evidence by identifying MTGMP-15783 as a "CPU MIPROM SC/MP II Board".

I have also used the MIPROM I troubleshooting guide for the more limited point that the corresponding P-15783 CPU card is illustrated in the guide. A TK Elevator spare-parts listing further identifies P-15783 as a refurbished Montgomery MIPROM CPU board, and the board photograph in that listing shows the processor package marked "INS8060N" and "ISP-8A/600N". However, I have not used the spare-parts photograph as the sole basis for the SC/MP claim; the main processor identification remains the Otis catalogue entry.

I have treated P-16782 cautiously. The MIPROM I troubleshooting guide lists P-15783 as a replacement for P-16782. The P-16782 board may also have used an SC/MP-family processor, since it is listed as replaceable by P-15783. However, I have not found a source that directly identifies the processor on P-16782, and the available MIPROM I guide illustrations are not clear enough to read the CPU package marking. I have therefore not described P-16782 as an SC/MP board in the article.

Please update/enhance as additional details become available.

We should likely remove the 1975 and first claims from the main page if they cannot be verified.

OldCPUs (talk) 22:46, 5 May 2026 (UTC)

You put a heck of a lot more thought into this than I have. The original text was this:

Montgomery Elevator Co of Moline IL (later purchased by KONE, Inc) used the SC/MP as the basis for its first micro processor based elevator controller released in 1975. There are still many of these units running in buildings across the USA.

As the text was uncited and I am not a fan of destructive edits, I looked for just one cite that could verify that an SC/MP was in some Montgomery Elevator design. A minimal effort. I like the detail though I think the justification might be best put in a note. RastaKins (talk) 14:00, 6 May 2026 (UTC)

@RastaKins ...

I must say thank you for the document you found and the reference you added. It was the missing link! as it referenced the PCB board number, which then revealed the other documents.

I'll look at moving some of the fuller explanations into the Notes to make the flow easier to read, and in a month remove the uncited date and "first" reference (although, honestly, I expect they might well be true, although I've not found a good citation for the SC/MP (I) availability date other than the dates on the manuals, which isn't concrete evidence of the chip availability date --- since manufacturers incorporating the chip into their products may have had early access to the chips before the finished manual). OldCPUs (talk) 19:10, 6 May 2026 (UTC)

Notes on Signetics and reported SC/MP second sources

These notes record the sourcing status behind the article wording on Signetics as an SC/MP second source.

• Osborne and Kane identified National Semiconductor as the prime source for SC/MP and Signetics as the authorized second source. The same source stated: "Although Signetics is authorized as an SC/MP second source, they have never actually manufactured SC/MP."

• Signetics did publish its own SC/MP II literature. The 1977 Signetics Bipolar/MOS Microprocessor Data Manual listed the ISP-8A/600 "Simple Cost Effective Microprocessor (SC/MP-II)" in its contents and included a Signetics-branded device section for the part.

• The front matter of the 1977 Signetics manual stated that it covered Signetics' "complete line of Bipolar and MOS Microprocessors" and that "This book contains a compilation of all products currently available." The same manual's contents listed the ISP-8A/600 SC/MP-II. This was treated as evidence of product-style Signetics literature for the SC/MP II, but not as proof that Signetics manufactured or shipped Signetics-marked SC/MP silicon.

• By 1982 the SC/MP II no longer appeared as a standalone product data-sheet entry in the contents of the Signetics MOS Microprocessor Data Manual. It appeared instead in application-note material: App Note M22, "Interface Techniques for the 2651 PCI", included an SC/MP II interface example and cited a "Signetics SC/MP II (ISP-8A/600) Microprocessor Specification".

• The App Note M22 itself was located. The item not located was a separate standalone copy of the exact "Signetics SC/MP II (ISP-8A/600) Microprocessor Specification" cited by M22.

• No examples of Signetics-marked SC/MP or SC/MP II processors were found in the collector materials checked or community discussions.

• T. D. Towers, Towers' International Microprocessor Selector, TAB Books, 1982, p. 205, was checked for additional second-source claims. It listed the original PMOS "SC/MP I FAMILY" as having "2nd source=none", but listed the NMOS "SC/MP II FAMILY" as having "2nd sources = Rockwell, Signetics, Western Digital". No supporting Rockwell or Western Digital manufacturer documentation or hardware examples were found, so they were treated as unresolved secondary-source leads only.

Sources checked:

• Adam Osborne and Gerry Kane, Osborne 4 & 8-Bit Microprocessor Handbook, Osborne/McGraw-Hill, 1981, p. 3-1.
• Signetics, Bipolar/MOS Microprocessor Data Manual, 1977, Chapter 2, ISP-8A/600-I section.
• Signetics, MOS Microprocessor Data Manual, January 1982, Section 6, "Interface Techniques for the 2651 PCI", App Note M22.
• T. D. Towers, Towers' International Microprocessor Selector, TAB Books, 1982, p. 205 - lists SC/MP I as having no second source, and SC/MP II second sources as Rockwell, Signetics, and Western Digital.

OldCPUs (talk) 07:51, 31 May 2026 (UTC)