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Summary
| Description |
English: Layout for the layers schematic for the silicon implementation of a six transistor SRAM memory cell. |
| Date | |
| Source | https://www.ijert.org/research/sram-memory-layout-design-in-180nm-technology-IJERTV4IS080677.pdf |
| Author | Praveen K N and B. G. Shivaleelavathi |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 09:10, 6 September 2019 | | 262 × 193 (18 KB) | Crystallizedcarbon | User created page with UploadWizard |
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